module TIMEG12K 
title 'Six-phase Master Timing Generator'

" Input and Output pins 
MCLK, RESET, RUN, RESTART                  pin;
T1, P1_L, P2_L, P3_L, P4_L, P5_L, P6_L     pin istype 'reg';
R1_L, R2_L, R3_L, R4_L, R5_L, R6_L         pin istype 'com';

" State definitions
PHASES  = [P1_L, P2_L, P3_L, P4_L, P5_L, P6_L];
NEXTPH  = [P6_L, P1_L, P2_L, P3_L, P4_L, P5_L];
SRESET  = [1, 1, 1, 1, 1, 1];
P1      = [0, 1, 1, 1, 1, 1];
OUTPUTS = [R1_L, R2_L, R3_L, R4_L, R5_L, R6_L];

equations

T1.CLK = MCLK; PHASES.CLK = MCLK;

WHEN RESET THEN {T1 := 1; PHASES := SRESET;}
ELSE WHEN (PHASES == SRESET) # RESTART THEN {T1 := 1; PHASES := P1;}
ELSE WHEN RUN & T1 THEN {T1 := 0; PHASES := PHASES;}
ELSE WHEN RUN & !T1 THEN {T1 := 1; PHASES := NEXTPH;}
ELSE {T1 := T1; PHASES := PHASES;}

!OUTPUTS = !PHASES & !T1;

end TIMEG12K