library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity Vcnttst is
    port (
        CLK: in STD_LOGIC;
        D: in UNSIGNED (3 downto 0);
        Q: out UNSIGNED (3 downto 0)
    );
end Vcnttst;

architecture Vcnttst_arch of Vcnttst is
signal IQ: UNSIGNED (3 downto 0);
begin
process (CLK, IQ)
  begin
    if CLK'event and CLK='1' then IQ <= IQ + 1; end if;
    Q <= IQ;     
  end process;
end Vcnttst_arch;