library IEEE;
use IEEE.std_logic_1164.all;

entity Vdlatch is
  port (D, C, CLR, PR: in STD_LOGIC;
        Q, QN: buffer STD_LOGIC );
end Vdlatch;

architecture Vdlatchc_b of Vdlatch is
begin
process(CLR, PR, C, D, Q, QN)
  begin
    if (CLR and PR) = '1' then Q <= '0'; QN <= '0';
    elsif CLR = '1' then Q <= '0'; QN <= '1';
    elsif PR = '1' then Q <= '1'; QN <= '0';
    elsif (C = '1') then Q <= D; QN <= not D;
    else Q <= Q; QN <= QN;
    end if;
  end process;
end Vdlatchc_b;