library IEEE;
use IEEE.std_logic_1164.all;

entity Vggame is 
  port ( CLOCK, RESET, G1, G2, G3, G4: in  STD_LOGIC;
         L1, L2, L3, L4, ERR:          out STD_LOGIC );
end;

architecture Vggame_arch of Vggame is
type Sreg_type is (S1, S2, S3, S4, SOK, SERR);
signal Sreg: Sreg_type;
begin

  process (CLOCK)
  begin
    if CLOCK'event and CLOCK = '1' then
      if RESET = '1' then Sreg <= SOK; else
        case Sreg is
          when S1 => if    G2='1' or G3='1' or G4='1' then Sreg <= SERR;
                     elsif G1='1'                     then Sreg <= SOK;
                     else                                  Sreg <= S2;
                     end if;
          when S2 => if    G1='1' or G3='1' or G4='1' then Sreg <= SERR;
                     elsif G1='1'                     then Sreg <= SOK;
                     else                                  Sreg <= S3;
                     end if;
          when S3 => if    G1='1' or G2='1' or G4='1' then Sreg <= SERR;
                     elsif G1='1'                     then Sreg <= SOK;
                     else                                  Sreg <= S4;
                     end if;
          when S4 => if    G1='1' or G2='1' or G3='1' then Sreg <= SERR;
                     elsif G1='1'                     then Sreg <= SOK;
                     else                                  Sreg <= S1;
                     end if;
          when SOK | SERR => if G1='0' and G2='0' and G3='0' and G4='0' 
                                 then Sreg <= S1; end if;
          when others => Sreg <= S1;
        end case;
      end if;
    end if;
  end process;      

  L1  <= '1' when Sreg = S1   else '0';
  L2  <= '1' when Sreg = S2   else '0';
  L3  <= '1' when Sreg = S3   else '0';
  L4  <= '1' when Sreg = S4   else '0';
  ERR <= '1' when Sreg = SERR else '0';

end Vggame_arch;